Investigating and Analyzing the Effect of Router Components on Network Performance on the Chip with Regard to Power Consumption
الموضوعات : Majlesi Journal of Telecommunication DevicesFarnaz Zogh 1 , Azadeh Alsadat Emrani Zarandi 2 , Vahid Sattari Naeini 3
1 - shahid bahonar university of kerman
2 -
3 -
الکلمات المفتاحية: Power Consumption, Network on chip, router architecture,
ملخص المقالة :
A network on the chip is a solution to connection problems compared with traditional-based chip which can fulfil multi-dimensional communication requirements. The router is a key component of the communication network which is referred as its backbone. Since the router occupies the largest area on the chip and it is the most widely used network component, in this paper, the architecture of the router in the network on the chip is examined and its roles with its components and their effect on the performance of the network are investigated, considering the parameters including time (delay), the area and more importantly the power consumption. It is shown that any modification, combination, or correction in any of the component effect on power consumption of the router and hence on the power consumption of the whole chip. To this end, the related works are examined to make an appropriate estimation of their analogy. This article will help researchers who are trying to design an optimal router based on power consumption.
[1] R. Afshar Mazayjani, M. Alaee, and F. Yazdanpanah, “Composition of Wired and Wireless Communications in Networks on Chip”, International Conference on Computer Engineering and Information Technology, 1395.
[2] K. Tatas, K. Siozios, D. Soudris, and A. Jantsch, “Designing 2D and 3D network-on-chip architectures” Springer, 2014.
[3] H. Elmiligi, M. Sallam, and M. W. El-Kharashi, “A power-optimized, area-efficient implementation of Connection-Then-Credit NoC physical layer” Microelectronics Journal, vol. 68, pp. 55-68, 2017.
[4] N. Kavaldjiev, G. J. M. Smit, and P. G. Jansen, “A virtual channel router for on-chip networks” in SOC Conference, 2004. Proceedings. IEEE International, 2004, pp. 289-293: IEEE.
[5] F.Zogh, M. Alaei, and F. Yazdanpanah “Architecture of Reconfigurable routers in NOC” the Fourth International Conference on New Findings of Science and Technology, 1396.
[6] F. Yazdanpanah, M. Alaee, and F.Zogh, “ Dynamic Reconfigurable Network On Chip” the Fourth International Conference on New Findings of Science and Technology, 1396.
[7] P. Mahr and C. Bobda, “Reconfigurable router for dynamic Networks-on-Chip” Rapid System Prototyping (RSP), 2010 21st IEEE International Symposium on, 2010, pp. 1-6: IEEE.
[8] C. Concatto, D. Matos, L. Carro, F. Kastensmidt, A. Susin, and M. Kreutz, “Noc power optimization using a reconfigurable router,” in NoC Power Optimization Using a Reconfigurable Router, 2009: IEEE.
[9] D. Matos, C. Concatto, M. Kreutz, F. Kastensmidt, L. Carro, and A. Susin, “Reconfigurable routers for low power and high performance,” IEEE Transactions on very large scale integration (VLSI) systems, vol. 19, no. 11, pp. 2045-2057, 2011.
[10] R. Kamal and J. M. M. Arostegui, “A Multi-Synchronous Bi-Directional NoC (MBiNoC) architecture with dynamic self-reconfigurable channel for the GALS infrastructure,” Alexandria Engineering Journal, 2017.
[11] B. Naraqi, Gh. Karimi, “Study on power consumption and power consumption reduction solutions in network on chip and test networks”, the first National Conference on Computer Engineering, Computer Science and Information Technology, Qom, June 1395, Applied Scientific University Qom governorate
[12] A. B. Kahng, B. Li, L.-S. Peh, and K. Samadi, “Orion 2.0: A power-area simulator for interconnection networks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 1, pp. 191-196, 2012.
[13] Xilinx, Xilinx Power Tools Tutorial, vol. UG733 (v1.0), March 15, 2010.
