Designing and Optimizing the Fetch Unit for a RISC Core
الموضوعات : Journal of Computer & Robotics
Bahman Javadi
1
(Computer Engineering and Information Technology Department, Amirkabir University of Technology, Tehran, Iran)
Mojtaba Shojaei
2
(Computer Engineering and Information Technology Department, Amirkabir University of Technology, Tehran, Iran)
Mohammad Kazem Akbari
3
(Computer Engineering and Information Technology Department, Amirkabir University of Technology, Tehran, Iran)
Farnaz Irannejad
4
(Computer Engineering and Information Technology Department, Amirkabir University of Technology, Tehran, Iran)
الکلمات المفتاحية: Instruction fetch, Branch prediction, Instruction cache, Cost, Performance, Timing,
ملخص المقالة :
Despite the extensive deployment of multi-core architectures in the past few years, the design and optimization of each single processing core is still a fresh field in computing .On the other hand, having a design procedure (used to solve the problems related to the design of a single processing core )makes it possible to apply the proposed solutions to specific-purpose processing cores .The instruction fetch, which is one of the parts of the architectural design, is considered to have the greatest effect on the performance .RISC processors, which have architecture with a high capability for parallelism, need a high instruction width in order to reach an appropriate performance .Accurate branch prediction and low cache miss rate are two effective factors in the operation of the fetching unit .In this paper, we have designed and analyzed the fetching unit for a 4-way( 4-issue )superscalar processing core .We have applied the cost per performance design style and quantitative approach to propose this fetch unit .Moreover, timing constrains are specially analyzed for instruction cache to enable the proposed fetch unit to be in a superpipeline system .In order to solve the timing problem, we have applied the division method to the branch prediction tables and the wave pipelining technique to the instruction cache.
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