Improved of Linearity Performance With low Common-mode Voltage Variations for Non-binary Successive Approximation ADC With a Monotonic Switching method
Subject Areas : Electronics Engineering
Nasrin Shayestehnezhad
1
,
عبدالرسول Ghasemi
2
1 - electrical engineering, Islamic Azad University, Bushehr Branch, Bushehr, Iran
2 - electrical engineering, Islamic Azad University, Bushehr Branch, Bushehr, Iran
Keywords:
Abstract :
In this paper, a fully differential successive approximation A/D converter is presented using the extended non-binary search algorithm with an accuracy of 10-bits, 11 comparison steps, and the sampling rate of 4.17MS/s which is suitable for low-power applications because it does not require to be calibration. In the non-binary search algorithm, there are overlaps between the search rang, that allow comparison decision errors to be digitally corrected. To improve the linear behavior of the proposed structure, a capacitive array D/A converter with non-binary weight is implemented, and the sampling frequency is increased compared to the conventional successive approximation converter through proper selection of non-binary capacitances of the capacitive array. The proposed structure operates based on monotonic switching logic. This switching method reduces the power consumption of DAC compared to conventional switching. The proposed structure is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, signal to noise and distortion ratio (SNDR) is 61.35dB, power consumption is 78.14µW, and figure of merit is 19.57(fj/Conv.step).
[1] A. H. Chang, H. S. Lee, and D. Boning, “A 12b 50MS/s 2.1mW SAR ADC with Redundancy and Digital Background Calibration,” in proc. IEEE ESSCIRC, Sept. 2013, pp. 109-112.
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[6] D.Zhang, and A. Alvandpour, “A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS,” IEEE Trans. Circuits & Syst. II ,vol.63 , no. 3, pp. 244-248, Mar. 2016.
[7] T. Ogawa, T. Matsuura , H. Kobayashi, N. Takai, M. Hotta, Hao San .et al, “ SAR ADC Algorithm with Redundancy and Digital Error Correction,” IEICE Trans. Fundamentals, vol.E93-A, no.2, pp.415- 423, Feb.2010.
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[9]S. Jiang, M. A. Do, K. S. Yeo, and W. M. Lim, “An 8-bit 200-MSample/s pipelined ADC with mixed-mode frontend S/H circuit,” IEEE Trans Circuits Syst I, vol. 55, no. 6, pp. 1430–1440, 2008.
[10] B.P. Ginsburg, and A.P. Chandrakasan ,“500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,” IEEE J. Solid-State Circuits, vol.42, no. 4, pp. 739-747, Apr. 2007.
[11]Y. K. Chang, C. S. Wang, and C. K. Wang, “A 8-bit 500 KS/s low power SAR ADC for bio-medical application,” in proc IEEE ASSCC Dig. Tech, Nov. 2007, pp. 228–231.
[12] C.Cheng Liu, S.Jyh Chang ,G.Ying Huang ,Y.Zu Lin “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, NO. 4,pp.731-740, APRIL 2010.
[13]A. M. Abo and Paul R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5,pp.599-606, May. 1999.
[14]A.R.Ghasemi ,M.Saberi , R.Lotfi , “A low-power capacitor switching scheme with low common-mode voltage variation for successive approximation ADC,” in Microelectronics Journal, vol.61,pp.15-20, Mar. 2017.
[15]D. Draxelmayr, “A 6 b 600 MHz 10 mW ADC array in digital 90 nm CMOS,” in proc.IEEE ISSCC Dig. Tech. Papers, 2004, pp. 264–265.
[16] G. Y. Huang, S. J. Chang, C. C. Liu, and Y. Z. Lin, “A 1μW 10bit 200kS/s SAR ADC with a bypass window for biomedical applications,” IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2783– 2794, Nov. 2012.
[17] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9uW at 1 MS/s," IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015,May.2010.
[18] S. Liu, Y. Shen, and Zh. Zhu, “A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching, ” IEEE Trans. Circuits & Syst.I, vol. 63, no.10, pp. 1616-1627, Oct.2016.
_||_[1] A. H. Chang, H. S. Lee, and D. Boning, “A 12b 50MS/s 2.1mW SAR ADC with Redundancy and Digital Background Calibration,” in proc. IEEE ESSCIRC, Sept. 2013, pp. 109-112.
[2]A. Arian, M. Saberi , S. Hosseini-Khayat, R. Lotfi, Y. Leblebici, “A 10-bit 50-MS/s Redundant SAR ADC with Split Capacitive-array DAC,” in Springer . Analog Integr CircSig Process, vol.71, pp. 586-589, June.2012.
[3] S. Haenzsche, S. Höppner, G. Ellguth, and R. Schüffny, “A 12-b 4 MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology,” IEEE Trans. Circuits Syst. II, vol. 61, no.11, pp. 835-839, Nov.2014.
[4] F. Kuttner, “A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13μm CMOS,” in proc.IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 176-177.
[5] D.Zhang, and A. Alvandpour,“Analysis and Calibration of Non-binary-Weighted Capacitive DAC for High-Resolution SAR ADCs,” IEEE Trans. Circuits &Syst. II ,vol.60, no. 9, pp. 666-670, Sep. 2014.
[6] D.Zhang, and A. Alvandpour, “A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS,” IEEE Trans. Circuits & Syst. II ,vol.63 , no. 3, pp. 244-248, Mar. 2016.
[7] T. Ogawa, T. Matsuura , H. Kobayashi, N. Takai, M. Hotta, Hao San .et al, “ SAR ADC Algorithm with Redundancy and Digital Error Correction,” IEICE Trans. Fundamentals, vol.E93-A, no.2, pp.415- 423, Feb.2010.
[8]C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, C. M. Huang, C. H. Huang, L. Bu, and C.C Tsai, “A 10b 100MS/s 1.13 mW SAR ADC with binary-scaled error compensation,” in proc IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010, pp. 386–387.
[9]S. Jiang, M. A. Do, K. S. Yeo, and W. M. Lim, “An 8-bit 200-MSample/s pipelined ADC with mixed-mode frontend S/H circuit,” IEEE Trans Circuits Syst I, vol. 55, no. 6, pp. 1430–1440, 2008.
[10] B.P. Ginsburg, and A.P. Chandrakasan ,“500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,” IEEE J. Solid-State Circuits, vol.42, no. 4, pp. 739-747, Apr. 2007.
[11]Y. K. Chang, C. S. Wang, and C. K. Wang, “A 8-bit 500 KS/s low power SAR ADC for bio-medical application,” in proc IEEE ASSCC Dig. Tech, Nov. 2007, pp. 228–231.
[12] C.Cheng Liu, S.Jyh Chang ,G.Ying Huang ,Y.Zu Lin “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, NO. 4,pp.731-740, APRIL 2010.
[13]A. M. Abo and Paul R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5,pp.599-606, May. 1999.
[14]A.R.Ghasemi ,M.Saberi , R.Lotfi , “A low-power capacitor switching scheme with low common-mode voltage variation for successive approximation ADC,” in Microelectronics Journal, vol.61,pp.15-20, Mar. 2017.
[15]D. Draxelmayr, “A 6 b 600 MHz 10 mW ADC array in digital 90 nm CMOS,” in proc.IEEE ISSCC Dig. Tech. Papers, 2004, pp. 264–265.
[16] G. Y. Huang, S. J. Chang, C. C. Liu, and Y. Z. Lin, “A 1μW 10bit 200kS/s SAR ADC with a bypass window for biomedical applications,” IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2783– 2794, Nov. 2012.
[17] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9uW at 1 MS/s," IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015,May.2010.
[18] S. Liu, Y. Shen, and Zh. Zhu, “A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching, ” IEEE Trans. Circuits & Syst.I, vol. 63, no.10, pp. 1616-1627, Oct.2016.
