Analysis of the effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder

Subject Areas : Electronics Engineering

Teimoor Rashedzadeh ¹ (Electrical Engineering, Islamic Azad University, Bushehr Branch, Bushehr, Iran)
Seyed Mohammad Ali Riyazi ² (Electrical Engineering, Islamic Azad University, Bushehr Branch, Bushehr, Iran)
Najmeh Cheraghi Shirazi ³ (department of electrical engineering, bushehr branch, islamic azad university, bushehr, iran)

Received: 2019-09-26 Accepted : 2019-12-17 Published : 2021-06-22

Keywords:

Abstract :

In this paper, full adder circuit with Hybrid-CMOS logic style is proposed which is a combination of pass transistors and transmission gates and N & P type transistors. For design full adder circuitry using FINFET transistors, BSIM-CMG model, Dual-gate and bulk FINFET structure using 16nm Gate length and HSPICE simulation. due to the structure and architecture of the FINFET transistors, the effect of changes in thickness and height and the number of FINs on the Drain current of the FINFET transistor and output parameters such as average power dissipation and propagation delay of the full adder cell and also the effect of changes in inputs frequency of full adder are investigated. According to the simulation results, with increasing thickness and height and the number of FINs, average power dissipation increases and propagation delay decreases, and vice versa. As well as increasing the operating frequency up, average power dissipation increases.

References:

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