Low offset comparator design in analog to digital 12-bit cyclic converter
Subject Areas : Electronics Engineering
Asghar Ebrahimi
1
(Islamic Azad University, Faculty member)
Mina Shirali
2
(Department of Electrical Engineering, Islamic Azad University, Bushehr Branch, Bushehr , Iran)
Keywords:
Abstract :
In this article, a high-speed analog-to-digital column-parallel converter with a small 12-bit resolution on both sides of the image sensor is proposed. This article also proposes a comparator with low offset. A method for accelerating the conversion speed using synchronization of variables (variable clock) and sampling capacitors have been developed. The pixel load amplifier achieves a light sensitivity of 9.19 V/lxs. The full signal size at the pixel output is 1/8V at the 3/3V power supply and the noise level is 1.8 and the dynamic signal amplitude is 60db. Finally, this circuit was simulated with HSPICE software and acceptable results were obtained. This circuit requires a voltage of 3.3V and is 0.35um in technology. Power consumption is 11 mW and SFDR is equivalent to 66dB, THD is equivalent to -2 and SNDR is equivalent to 40dB.
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[1] O.Y. Pecht, A. Belenky, “Autoscaling CMOS APS with CustomizedIncrease of Dynamic Range,” ISSCC Dig. Tech. Papers, pp. 100-101, Feb.,2008
[2] W. Bidermann, A. E. Gamal, S. Ewedemi, J. Reyneti, H. Tian, D. Wile,D. Yang, “A 0.18m High Dynamic Range NTSC/PAL Imaging System-ona-Chip with Enhanced DRAM Frame Buffer,” ISSCC Dig. Tech. Papers, pp.212-213, Feb., 2007.
[3] O.Y. Pecht, A. Belenky, “Autoscaling CMOS APS with CustomizedIncrease of Dynamic Range,” ISSCC Dig. Tech. Papers, pp. 100-101, Feb.,2008.
[4] Steven Decker, R. Daniel McGrath, Kevin Brehmer, Gharles G. Sodini,“A 256 x 256 CMOS Imaging Array with Wide Dynamic Range Pixels andColumn-Parallel Digital Ouput”, IEEE J. Solid-State Circuits, 33, no. 12,pp. 2081-2091, 2009.
[5] S. H. Lewis and P.R.Gray, “A Pipelined 5-MSample/s 9-bit Analog-to-Digital Converter,’’ IEEE J. Solid-State Circuits, pp. 954-961, vol. SC-22,2010.
