Computational Circuit Design Using a New Seven-Input Majority Gate in Quantum-dot Cellular Automata

Subject Areas : Renewable energy

Farzaneh Jahanshahi Javaran ¹ (Department of Computer Engineering- Science and Research Branch, Islamic Azad University, Tehran, Iran.)
Somayyeh Jafarali Jassbi ² (Department of Computer Engineering- Science and Research Branch, Islamic Azad University, Tehran, Iran.)
Hossein Khademolhosseini ³ (Department of Computer Engineering- Beyza Branch, Islamic Azad University, Beyza, Iran)
Razieh Farazkish ⁴ (Department of Computer Engineering- South Tehran Branch, Islamic Azad University, Tehran, Iran)

Received: 2022-02-20 Accepted : 2022-07-16 Published : 2024-11-21

Keywords: Fault tolerance, Quantum-dot cellular Automata, Nano-electronics, seven-input Majority Gate, simulator software,

Abstract :

The quantum-dot cellular automata (QCA) technology is a computational technology used to build nano-scale circuits. When the dimensions of the components decrease, the sensitivity of the circuit increases and the quantum circuits become more vulnerable to the occurrence of defects and radiation in the environment. The two major gates in this technology are inverter and majority gates, and most circuits are built based on these two gates. This paper aimed to design a seven-input majority gate in quantum-dot cellular automata by imposing low overhead on the circuit. Using a majority gate with more inputs reduces cell count, latency, and complexity in the QCA circuit. However, perhaps the need to use the seven-input gate is not yet felt we then design and implement a number of logic circuits. A new 7-input majority gate is designed in this paper, with 19 cells. The proposed structure is single-layer with an occupied area of 24564 nm2 that produces the correct output in one clock phase, then a four-input AND gate, a four-input OR gate, a two-input XOR gate, a two-input XNOR, a three-input XOR gate and a full adder are implemented using the designed seven-input gate. Including all multi-bit full adders, using the proposed seven-input gate. The proposed full adder is designed by the seven-input majority gate proposed and a fault-tolerant three-input majority gate. Therefore, it can be said that the designed full adder is somewhat tolerable, that means, it is somewhat tolerable against the fault that occur in this technology. QCAPro software is used to analyze the energy consumption of the recommended structure. Then, the circuit performance is evaluated using QCADesigner 2.0.3 simulator software for quantum-dot cellular automata.  

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