A 27-31 GHz CMOS LNA for 5G Application via Improved Noise Cancellation Technique and Gain Boosting

محورهای موضوعی : مهندسی هوشمند برق

Seyed Alborz Hosseini ¹ , Mahmoud Mohammad Taheri ² , Ramin Khosravi ³ , Gholamreza Moradi ⁴

1 - Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran
2 - School of Electrical and computer Engineering, College of Engineering, University of Tehran, Tehran, Iran
3 - Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran
4 - Electrical Engineering Department, Amirkabir University of Technology, Tehran, Iran

تاریخ دریافت : 1400/07/18 تاریخ پذیرش : 1400/08/29 تاریخ انتشار : 1400/12/10

کلید واژه: LNA, mm-wave, 5G, Noise Cancelation,

چکیده مقاله :

In this paper, a novel LNA design based on improved noise cancellation technique in the frequency range of 27 to 31 GHz.is presented The proposed LNA is suitable for millimeter wave 5G wireless communication. The first stage of this two-stage LNA is designed with noise cancelation approach to decrease the noise figure of the system. In order to improve the design method, we utilizes a negative feedback by implementing a couple inductor with a transformer connection. The negative feedback provides an acceptable input matching and control the gain to increase the band width. The cascode structure is used in the second stage for its higher gain and stability and better reverse isolation at millimeter wave frequency. Furthermore, an inductor is utilized to boost the gain with neutralizing the capacitance of node between two transistors in a cascode structure. The CMOS silicon on insulator (SOI) is utilized to provide a high level of integration and low power consumption with the minimum cost. The proposed LNA is designed with 130 nm CMOS technology and has 22.14 dB gain with 1.86 dB noise figure at 29 GHz. The 3-dB bandwidth of the designed LNA is 4 GHz (14%) and its DC power consumption is 33.4 mW. The IIP3 is -16dBm and input reflection coefficient is better than -10dBm in the frequency range of interest. The proposed LNA is simulated by ADS software.

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A 27-31 GHz CMOS LNA for 5G Application via Improved Noise Cancellation Technique and Gain Boosting

Seyed Alborz Hosseini a, Mahmoud Mohammad-Taheri b, Ramin Khosravi a, Gholamreza Moradi c

 

a Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran

b School of Electrical and computer Engineering, College of Engineering, University of Tehran, Tehran, Iran

cElectrical Engineering Department, Amirkabir University of Technology, Tehran, Iran

Abstract—In this paper, a novel LNA design based on improved noise cancellation technique in the frequency range of 27 to 31 GHz.is presented The proposed LNA is suitable for millimeter wave 5G wireless communication. The first stage of this two-stage LNA is designed with noise cancelation approach to decrease the noise figure of the system. In order to improve the design method, we utilizes a negative feedback by implementing a couple inductor with a transformer connection. The negative feedback provides an acceptable input matching and control the gain to increase the bandwidth. The cascode structure is used in the second stage for its higher gain and stability and better reverse isolation at millimeter wave frequency. Furthermore, an inductor is utilized to boost the gain with neutralizing the capacitance of node between two transistors in a cascode structure. The CMOS silicon on insulator (SOI) is utilized to provide a high level of integration and low power consumption with the minimum cost. The proposed LNA is designed with 130 nm CMOS technology and has 22.14 dB gain with 1.86 dB noise figure at 29 GHz. The 3-dB bandwidth of the designed LNA is 4 GHz (14%) and its DC power consumption is 33.4 mW. The IIP3 is -16dBm and input reflection coefficient is better than -10dBm in the frequency range of interest. The proposed LNA is simulated by ADS software.   Keywords—LNA, mm-wave, 5G, Noise Cancelation.

 

 

1.       Introduction

Recently, the demand for high data rate has being dramatically increased. Therefore, the 5G wireless communication is being made headway to surmount this demand. Due to large available bandwidth, the mm-wave spectrum is chosen as a robust candidate. World regulation agencies have recommended several possible mm-wave frequency bands which includes 28, 37, and 39 GHz by the Federal Communications Commission (FCC) in USA[1]. Consequently, the frequency around 29 GHz is selected due to its minimum atmospheric absorption[2]. 

The most significant part of a millimeter wave receiver is low noise amplifier (LNA). In fact, the overall noise figure of a receiver is determined by LNA noise figure as is evidenced from the Friis formula. As the design of a LNA is challenging task, the researchers have studied on the several features of LNA such as gain, noise figure (NF), bandwidth, linearity, power consumption and etc. in the recent year [3]. Eventually, there is a trade of between different features. In this paper, the proposed techniques concentrates on decreasing the noise figure, increasing the gain and linearity, while other characteristics are being kept in the appropriate levels.

This is necessary to choose the best technology for the implementation of a LNA. Due to its high level of integration, low cost and low power consumption compared with those of the III-V semiconductor technology, the CMOS silicon on insulator (SOI) has attracted the researchers [4].

Some recent research works in LNA around the 29 GHz are as follows.

In [4], Mohd Hassan et al. proposed a novel LNA using different transistor layouts. The LNA with multifinger double-gate transistor provides a gain of 3.77 dB at 38.5 GHz. In [5], Keshavarz et al. presented a new LNA with emphasis on the optimization layout techniques for passive and active elements .In [6], Ding et al. presented a compact low-noise amplifier using transformer-based noise reduction and single-ended neutralization approach at 24-GHz. A LNA is proposed with three differential amplifier stages in which the proposed amplifier utilized the -boost technique based on capacitor cross-coupled in 24-30 GHz [3]. In [7], a LNA has been designed by cascode topology to achieved NF of around 1.5 dB at 28 GHz by CMOS process. In [8], Wu et al. proposed an LNA using a differential -boosted common-gate (CG) stage. A transformer inter-stage couple network is utilized to increase the amplifier bandwidth. Wu et al. presented a K-band low-noise amplifier using a 3-stage cascode structure in a 0.13-μm RF CMOS. In [9], the amplifier gain is 31.2 dB at 24 GHz.  All published papers have concentrated on some of LNA parameters while trading off between them.

The demand for the high data rate is the motivation for a new millimeter wave LNA design presented in this paper. Our LNA has a better figure of merit compared with that of obtained in the recent publications.

In this paper a two-stage LNA in a TSMC 0.13-μm CMOS technology is presented. The first stage is designed by a noise cancellation topology for minimizing the noise figure while maximizing the gain. The second stage has utilized the gain boosting technique by implementing the cascode topology. In the following section, the design procedure for the proposed LNA is discussed.

2.       Noise Cancellation

Noise cancellation technique is implemented to minimize the low noise figure and improve the input impedance matching [9]. There are two noise cancellation topologies that include the common source (CS) and common gate (CG). CG is more common because it has a better input matching than that of CS and has been widely used in low frequency although some papers are published at the frequency of higher than 20 GHz [10, 11]. Fig.1 (a) shows a CG structure used for the noise cancellation technique.

 

 

 

 

 

 

 

 

 

 

 

Fig. 1 a) The topology of a typical noise cancellation used in high frequency b) The proposed LNA circuit based on the noise cancellation.

 

In Fig.1 (a), the thermal noise of  is passing from two paths. The first path, averages the drain noise current  passes through and produces  with negative phase. The second path is through  and changes the phase of the noise current. Besides, voltage in  has positive phase. The equation 1 shows the values of nod’s voltages.

(1)

Eventually, the thermal noise is minimized by minimizing the difference between  and  and will be cancelled if . Therefore, equation (2) is necessary to eliminate the  thermal noise.

(2)

 By removing the, the system noise figure is decreased while the gain is suitable. However the transistor still produces the noise that should be controlled.

Base on this concept we proposed a circuit which utilizes a couple inductor with a transformer connection that acts as a negative feedback as shown in Fig. 1 (b). This structure is used for input matching and controlling the gain and expanding the bandwidth. Fig. 2 (b) shows the proposed circuit for small signal analysis.

 

Fig. 2 a) A common gate with transformer feedback b) The circuit small signal model.

 

Based on Fig. 2 (b) and ignoring the channel resistor, the circuit input impedance can be obtained as follows:

(3)
(4)

whereand   are coupling coefficient and turns ratio respectively. Combining the equation (3) with (4) and also removing the first part of equation (4), the circuit input impedance is expressed as (5) due to resonating the with.

(5)

In the following, the proposed circuit gain is calculated. According to the equation (6) as:

(6)

and assuming the input matching:

(7)

The circuit gain of Fig. 2 is achieved as below:

 

(8)

Additionally, the noise factor ignoring the effect of the transistor is:

 

(9)

The equation (9) shows that the proposed circuit noise figure is independent ofand lower than that of a typical noise cancellation circuit.

3.       Proposed LNA circuit

After proposing the novel technique that lead to reduce the noise figure while controlling the gain by  to expand the bandwidth, in this paper a two-stage amplifier is designed to boost the gain.  The second stage has a cascade topology. This structure has a higher gain and better reverse isolation and stability at mm-wave frequency compared to those of the conventional common source, [5]. As seen in Fig. 3, the gain boosting is used to improve the gain. A positive feedback to  is provided by adding  in [13]. It increases the voltage across and also the drain current of . Finally, the transistor transconductance increases which boosts the total gain. Moreover, adding inductor  neutralizes the capacitance at source node of  to boost the gain [12-14]. Eventually by coupling two LNA stages that the first stage reduces the noise figure and increases the bandwidth while the second stage increases the gain the design is completed. In addition other LNA parameters are kept in an acceptable values. 

 

 

Fig. 3 The proposed LNA based on noise cancelation and gain boosting technique

 

The simulated results for the designed amplifier will be discussed in the following section.

4.       Design and Simulation results

The ADS software has been implemented to design and simulate the proposed LNA in mm-wave. Advanced CMOS technology gives an opportunity to design a LNA with lower noise figure and higher gain. However, one of design parameter is cost. Therefore in this paper 130 nm CMOS technology is used to minimize the cost for the LNA design. From the equations presented in the previous sections, for the first stage the gate width is chosen to be  for the maximum gain and input matching while for the second stage the gate width for  is . The gate width for the transistor  is set to the lowest possible value of  in order to decrease the thermal noise. The, and  act as tuner, matching component and gain controller in LNA, and their values are 135, 115 and 142 pH respectively.

 

Fig. 4 The effect of  on the gain

 

Fig. 4 shows that the gain decrease by increasing. However increasing improves the bandwidth and flattens the gain.

In the second stage, and  which is a gain booster is 109 pH. Fig.5 shows the effect of  on the system gain.

 

Fig. 5 The effect of on the gain

 

The parameters of the proposed designed amplifier are shown in Table 1. The layout of proposed LNA is designed by cadence with TSMC 130 nm technology (Fig. 10).

5.       Results

 As Fig. 6 shows, the proposed LNA has a 22.1 dB gain at 29.1 GHz. The 3-dB bandwidth is 4 GHz from 26.8 to 30.8 GHz (14%). The noise figure is 1.86 dB at 29.2GHz as expected (Fig. 7). This noise figure which

Table 1 The parameters of proposed LNA
	115		109
	142		109
	135		112
	210		330
	150		350
	190		380
	53		30
	28		33

 

is achieved in CMOS technology is based on our knowledge the lowest value at around 29 GHz by this technology compared with that of achieved by recent published papers. 

Fig. 8 and Fig. 9 show the S-parameters and IIP3 results of the designed LNA. As can be seen from this figures,  is better than -10 dB in 27 to 30.4 GHz frequency range and IIP3 is around -16dBm. Furthermore by implementing 1.2 V power supply, the DC power consumption is 33.4 mW 

 

Fig. 6 The gain of proposed LNA

 

 

Fig. 7 The noise figure of the proposed LNA

 

To compare the performance of our designed amplifier, we have defined three figures of merit which are presented in 10 and 11. The results of the comparison are shown in Table 2. As can be seen from this Table, the superiority of the proposed designed amplifier is evidence.

 

 

 

Fig. 8 The S- parameters of proposed LNA

 

 

 

	(10)
	(11) [15]

 

 

 

Fig. 9 The linearity (IIP3) of proposed LNA

 

 

Fig. 10 The layout of proposed LNA

6.       Conclusion

In this paper a novel LNA design is proposed. This proposed LNA is a two-stage amplifier in which the first stage utilized a noise cancelation circuit to reduce the noise figure. Additionally in this stage, a negative feedback with transformer structure has used to improve the bandwidth. In the second stage a cascode topology with gain boosting technique is used to provide a good isolation and increase the LNA gain. Beside an inductor is added to neutralize the capacitance of source node in transistor for improving the gain. The results showed a 22.14 dB gain and 1.86 dB noise figure at 29 GHz. This values are obtained from ADS simulation.

 

 

 

			Table 2  Comparison between this work and the LNAs that have been published recently
Reference		[11]		[5]	[16]	[6]	[15]	[4]	[17]	This work
Year		2018		2018	2019	2019	2015	2016	2019	2021
Frequency(GHz)		23-30		33	30-34.5	24	46	35.5-41.9	24	26.8-30.8
Topology		2-Noise cancellation & CS		2-Cascode	2- diff	2-stage	2-Noise cancellation	5- CS	3- cascode	2-Noise cancellation & Cascode
Process(CMOS)		28 nm		28 nm	65 nm	65 nm	90 nm	130 nm	130 nm	130 nm
Gain(dB)		17.7		24.5	20.8	23.5	10.2	13.8	31.2	22.14
NF(dB)		4.8		4	3.71	3.3	6.5	4.2	4.9	1.86
IIP3(dBm)		*		-15.9	-10.8	*	-2.4	*	*	-16
(mW)		22.2		27.6	26.7	12	13.8	30.9	22.3	33.4
Area( )		0.31		0.23	0.39	0.15	0.42	0.98	0.53	0.73
BW(GHz)		7		4.4	4.5	3	10.2	6.4	1.7	4
FOM1		32.6		35.9	34.5	30.65	19.05	27.6	13.6	102
FOM2		1.46		1.3	1.29	2.55	1.38	0.89	0.06	3.05

 

 

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