Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor

محورهای موضوعی : فصلنامه نانوساختارهای اپتوالکترونیکی

Mahsa Roohy ¹ (Department of Electrical Engineering, Khoy Branch, Islamic Azad University, Khoy, Iran)
Reza Hosseini ² (Department of Electrical Engineering, Khoy Branch, Islamic Azad University, Khoy, Iran)

تاریخ دریافت : 1398/01/11 تاریخ پذیرش : 1398/03/21 تاریخ انتشار : 1398/02/11

کلید واژه: Heterojunction GAA NW TFET, Silicon GAA NW TFET, On-State, Off-State, Cut-Off Frequency,

چکیده مقاله :

In this paper, we have presented a heterojunction gate all around nanowire
tunneling field effect transistor (GAA NW TFET) and have explained its characteristics
in details. The proposed device has been structured using Germanium for source region
and Silicon for channel and drain regions. Kane's band-to-band tunneling model has
been used to account for the amount of band-to-band tunneling generation rate per unit
volume of carriers which tunnel from valence band of source region to conduction band
of channel. The simulations have been carried out by three dimensional Silvaco Atlas
simulator. Using extensive device simulations, we compared the results of presented
heterojunction structure with those of Silicon gate all around nanowire TFET. Whereas
due to thinner tunneling barrier at the source-channel junction which leads to the
increase of carrier tunneling rate, the heterojunction gate all around nanowire TFET
shows excellent characteristics with high on-state current, superior transconductance
and high cut-off frequency.

منابع و مأخذ:

[1] D. Lizzit, P. Palestri, D. Esseni, A. Revelant, L. Selmi. Analysis of the
Performance of n-Type FinFETs with Strained SiGe Channel. IEEE
Transaction on Electron Devices, 60(6) (2013) 1884-1891. available:
https://ieeexplore.ieee.org/document/6515165
[2] R. Hosseini, M. Fathipour, R. Faez. A comparative study of NEGF and
DDMS models in the GAA silicon nanowire transistor. International Journal
of Electronics. 99(9) (2012) 1299–1307. available:
https://www.tandfonline.com/doi/abs/10.1080/00207217.2012.669709
[3] Ch. Lee, I. Ferain, A. Afzalian, R. Yan, N. Dehdashti, P. Razavi, J. Colinge,
Performance estimation of junctionless multigate transistors, Solid-State
Electronics. 54(2) (2010) 97–103. Available:
https://www.sciencedirect.com/science/article/pii/S0038110109003463
[4] K. Pourchitsaz, M. R. Shayesteh, Self-heating effect modeling of a carbon
nanotube-based fieldeffect transistor (CNTFET), Journal of
Optoelectronical Nanostructures. 4(1) (2019) 51-66. Available:
http://jopn.miau.ac.ir/article_3385.html
[5] M. Akbari Eshkalak, R. Faez, A Computational Study on the Performance
of Graphene Nanoribbon Field Effect Transistor, Journal of
Optoelectronical Nanostructures, 2(3) (2017) 1-12.Available:
http://jopn.miau.ac.ir/article_2427.html
[6] M. Nayeri, P. Keshavarzian, M. Nayeri, A Novel Design of Penternary
Inverter Gate Based on Carbon Nano Tube, Journal of Optoelectronical
Nanostructures, 3(1) (2018) 15-26. Available:
http://jopn.miau.ac.ir/article_2820.html
[7] A. Rezaei, B. Azizollah-Ganji, M. Gholipour, Effects of the Channel
Length on the Nanoscale Field Effect Diode Performance, Journal of
Optoelectronical Nanostructures, 3(2) (2018), 29-40. Available:
http://jopn.miau.ac.ir/article_2862.html
[8] P. Bal, B. Ghosh, P. Mondal, M. Akram, B. Mukund, M. Tripathi. Dual
material gate junctionless tunnel field effect transistor. Journal of
Computational Electronic, 13(1) (2014) 230–234. Available:
https://link.springer.com/article/10.1007/s10825-013-0505-4
[9] M. Raushan, N. Alam, M. Siddiqui. Performance Enhancement of
Junctionless Tunnel Field Effect Transistor Using Dual-k Spacers. Journal
of Nanoelectronics and Optoelectronics, 13(6) (2018) 1–9. Available:
https://www.ingentaconnect.com/contentone/asp/jno/2018/00000013/00000
006/art00016
[10] D. Xiao, X. Wang, Y. Yu, J. Chen, M. Zhang, Z. Xue, J. Luo, TCAD study
on gate-all-around cylindrical (GAAC) transistor for CMOS scaling to the
end of the roadmap. Microelectronic Journal, 40(12) (2009) 1766–1771.
Available:
https://www.sciencedirect.com/science/article/abs/pii/S0026269209001815
[11] M. Cheralathan, A. Cerdeira, B. Iniguez, Compact model for long-channel
cylindrical surrounding-gate MOSFETs valid from low to high doping
concentrations. Solid-State Electronics. 55(1) (2011)13–18. Available:
https://www.sciencedirect.com/science/article/pii/S0038110110003266
[12] R. Hosseini, M. Fathipour, R. Faez. Quantum simulation study of gate-allaround
(GAA) silicon nanowire transistor and double gate metal oxide
semiconductor field effect transistor (DG MOSFET). International Journal
of the Physical Sciences, 7(28) (2012) 5054-5061. Available:
https://academicjournals.org/journal/IJPS/article-abstract/B27116C16368
[13] M. Rahimian, M. Fathipour. Junctionless nanowire TFET with built-in NP-
N bipolar action: Physics and operational principle. Journal of Applied
Physics, 120(22) (2016) 225702. Available:
https://aip.scitation.org/doi/abs/10.1063/1.4971345?journalCode=jap
[14] M. Rahimian., M. Fathipour. Asymmetric junctionless nanowire TFET with
built-in n+ source pocket emphasizing on energy band modification.
Journal of Computational Electronics. 15(4) (2016) 1297-1307. Available:
https://link.springer.com/article/10.1007%2Fs10825-016-0895-1
A. Verhulst, W. Vandenberghe, K. Maex, G. Groeseneken. Boosting the
on-current of a n-channel nanowire tunnel field-effect transistor by source
material optimization. Journal of Applied Physics, 104(6) (2008) 064514.
Available: https://aip.scitation.org/doi/10.1063/1.2981088
[15] S. Marjani, S. E. Hosseini, R. Faez. A 3D analytical modeling of tri-gate
tunneling field-effect transistors. Journal of Computational Electronics.
15(3)(2016) 820–830.
Available: https://link.springer.com/article/10.1007/s10825-016-0843-0
[16] R. Molaei Imen Abadi, S. A. Sedigh Ziabari. Representation of type I
heterostructure junctionless tunnel field effect transistor for highperformance
logic application. Applied Physics A. 122 (2016) 616.
Available:
https://link.springer.com/article/10.1007/s00339-016-0151-3
[17] E. Kurniawan, Sh. Yang, V. Thirunavukkarasu, Y. Wu. Analysis of Ge-Si
Heterojunction Nanowire Tunnel FET: Impact of Tunneling Window of
Band-to-Band Tunneling Model. Journal of The Electrochemical Society.
164 (11) (2017) E3354-E3358.
Available: http://jes.ecsdl.org/content/164/11/E3354.abstract
[18] J. Huang, P. Long, M. Povolotskyi, H. Ilatikhameneh, T. Ameen, R.
Rahman, R. Rodwell, G. Klimeck. A Multiscale Modeling of Triple-
Heterojunction Tunneling FETs. IEEE Transaction on Electron Devices.
64(6) (2017) 2728-2735.
Available: https://ieeexplore.ieee.org/document/7898786
[19] R. Molaei Imen Abadi, S. A. Sedigh Ziabari. Representation of strained
gate-all around junctionless tunneling nanowire filed effect transistor for
analog applications. Microelectronic Engineering. 162 (2016) 12–16.
https://www.sciencedirect.com/science/article/abs/pii/S0167931716302179
[20] Q. Zhao, S. Richter, Ch. Schulte-Braucks, L. Knoll, S. Blaeser, G. Luong,
S. Trellenkamp, A. Schafer, A. Tiedemann, J. Hartmann, K. Bourdelle, S.
Mantl. Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog
Applications. IEEE Journal of the Electron Devices Society. 3(3)
(2015)103-114.
Available: https://ieeexplore.ieee.org/abstract/document/7031858/
[21] Silvaco Int.: ATLAS User’s Manual, Device simulation Software, Silvaco
International, Santa Clara (2016)
[22] A. Schenk. Finite-temperature full random-phase approximation model of
band-gap narrowing for silicon device simulation. Journal of Applied
Physics, 84(7) (1998) 3684- 3694.
Available: https://aip.scitation.org/doi/10.1063/1.368545
[23] A. Richter, S.W. Glunz, F. Werner, J. Schmidt, A. Cuevas. Improved
quantitative description of Auger Recombination in crystalline silicon,
Physical Review B, 86(2012) 165202.
Available:
https://journals.aps.org/prb/abstract/10.1103/PhysRevB.86.165202
[24] W. Shockley, W. Read. Statistics of the Recombination of Holes and
Electrons. Physical Review. 87(1952) 835-842.
Available: https://journals.aps.org/pr/abstract/10.1103/PhysRev.87.835
[25] R. N. Hall. Electron Hole Recombination in Germanium. Physical Review.
87(1952) 387.
Available: https://journals.aps.org/pr/abstract/10.1103/PhysRev.87.387
[26] M. G. Bardon, H. P. Neves, R. Puers, Ch. V. Hoof. Pseudo twodimensional
model for double-gate tunnel FETs considering the junctions
depletion regions. IEEE Transaction on Electron Devices. 57(4) (2010)
827–834.
Available: https://ieeexplore.ieee.org/document/5415671
[27] E. Kane. Theory of tunneling. Journal of Applied Physics. 32(1) (1961)
83–91.
Available: https://aip.scitation.org/doi/10.1063/1.1735965
[28] E. Kane. Zener tunneling in semiconductors. Journal of Physics and
Chemistry of Solids. 12(2) (1961)181–188. Available:
https://www.sciencedirect.com/science/article/abs/pii/0022369760900354
Performance Study and Analysis of Heterojunction Gate All Around Nanowire … * 27
[29] N. Bagga, S. Dasgupta. Surface Potential and Drain Current Analytical
Model of Gate All Around Triple Metal TFET. IEEE Transaction on
Electron Devices. 64 (2)(2017) 606 – 613.
Available: https://ieeexplore.ieee.org/document/7807255
[30] H. Kao, A. Verhulst, W. Vandenberghe, B. Soree, B. Groeseneken, K.
Meyer. Direct and Indirect Band-to-band Tunneling in Germanium-based
TFETs. IEEE Transaction on Electron Devices. 59(2) (2012) 292–30.
Available: https://ieeexplore.ieee.org/abstract/document/6096396/