In this paper, we have presented a heterojunction gate all around nanowire
tunneling field effect transistor (GAA NW TFET) and have explained its characteristics
in details. The proposed device has been structured using Germanium for source region
and Silicon for channel and drain regions. Kane's band-to-band tunneling model has
been used to account for the amount of band-to-band tunneling generation rate per unit
volume of carriers which tunnel from valence band of source region to conduction band
of channel. The simulations have been carried out by three dimensional Silvaco Atlas
simulator. Using extensive device simulations, we compared the results of presented
heterojunction structure with those of Silicon gate all around nanowire TFET. Whereas
due to thinner tunneling barrier at the source-channel junction which leads to the
increase of carrier tunneling rate, the heterojunction gate all around nanowire TFET
shows excellent characteristics with high on-state current, superior transconductance
and high cut-off frequency. تفاصيل المقالة

A new side-contacted field effect diode (S-FED) structure has been
introduced as a modified S-FED, which is composed of a diode and planar double gate
MOSFET. In this paper, drain current of modified and conventional S-FEDs were
investigated in on-state and off-state. For the conventional S-FED, the potential barrier
height between the source and the channel is observed to become larger and the flow of
injected electrons is reduced. Thus, the drain current decreases in on-state. While in offstate,
the potential barrier height and width become smaller in conventional S-FED and
so the drain current is greater than that of modified structure. Mixed mode simulations
were used to determine the performance of the proposed logic gates. We compared the
operation of modified S-FED with that of conventional S-FED. Simulated power delay
product (PDP) of the modified S-FED-based NOR, NAND, XOR gates were found to
be about 416fJ, 408fJ and 336fJ, respectively, compared with 906fJ, 810fJ and 705fJ
achievable with conventional S-FED logic gates. تفاصيل المقالة

Abstract:
 We purpose a hybrid energy harvester made of silicon solar cell, piezoelectric and thermoelectric. Our simulations are carried out using the COMSOL software. For this purpose, MEMS, heat transfer and electromagnetic modules were used. We connected nine piezoelectric, one thermoelectric and one solar cell modules in series to maximize the harvested energy and provide the appropriate voltage level. It is observed that the maximum electric current and voltage is about 200mA and 5V, respectively, which is equivalent to approximately 1W. The total obtained energy was amplified by two DC/DC converters and the voltage level increased to 5V.  Also, we theoretically proved that the use of an optical window (as top and bottom contact layers) based on photonic multilayer can control surface reflection. It is found that if we use two contact layers in the front and back of the solar cell, the transmittance increases from 33% (without contact layer) to 67% (with double contact layer). تفاصيل المقالة