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مقاله
1 - طراحی شبکه عصبی کانولوشن با وزنهای موثر با استفاده از الگوریتم ژنتیک برای طبقه¬بندی تصاویرتحلیل مدارها، داده ها و سامانه ها , شماره 5 , سال 2 , بهار 1403شبکههای عصبی کانولوشن مهمترین شاخه یادگیری عمیق هستند و در سالهای اخیر، توسعه سریعی را تجربه کرده¬اند. یک چالش عمده در استفاده از این شبکهها، تعداد زیاد پارامترهای آن¬هاست که منجر به هزینههای محاسباتی و زمانی بالا در برنامههای کاربردی دنیای واقعی میشود. در بسیاری چکیده کاملشبکههای عصبی کانولوشن مهمترین شاخه یادگیری عمیق هستند و در سالهای اخیر، توسعه سریعی را تجربه کرده¬اند. یک چالش عمده در استفاده از این شبکهها، تعداد زیاد پارامترهای آن¬هاست که منجر به هزینههای محاسباتی و زمانی بالا در برنامههای کاربردی دنیای واقعی میشود. در بسیاری از موارد، این افزایش هزینهها به دلیل طراحی شبکههای عمیقتر با پارامترهای بیشتر برای دستیابی به دقت بالاتر است. مقاله حاضر از الگوریتمهای تکاملی برای معرفی روشی استفاده کرده که میتواند بهترین وزنها را شناسایی کرده و از آنها برای ساخت شبکههای دقیقتر استفاده کند؛ در نتیجه نیاز به شبکههای عمیقتر را از بین میبرد. در پایان مقاله، شبکه¬ی به دست آمده از الگوریتم پیشنهادی با بهترین شبکههای موجود مقایسه شده است که نشان می¬دهد شبکه¬ی پیشنهادی دقت طبقه¬بندی را افزایش داده است؛ در حالیکه تعداد پارامترهای آن بسیار کمتر است و در نتیجه، باعث صرفه¬جویی در منابع محاسباتی و زمان میشود. پرونده مقاله -
مقاله
2 - A New Analysis, Design and Fabrication of DVB-T/T2 LDMOS UHF Broadband AmplifierMajlesi Journal of Telecommunication Devices , شماره 35 , سال 9 , تابستان 2020In this paper we want to design linear amplifiers for the Multi Frequency Network (MFN) or Single Frequency Network (SFN) digital terrestrial applications for Digital Video Broadcasting-Terrestrial (DVB-T/T2) transmitters with frequencies of 400 to 900 MHz, so to achiev چکیده کاملIn this paper we want to design linear amplifiers for the Multi Frequency Network (MFN) or Single Frequency Network (SFN) digital terrestrial applications for Digital Video Broadcasting-Terrestrial (DVB-T/T2) transmitters with frequencies of 400 to 900 MHz, so to achieve this aim, we have used Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor technology has been used. The RF input signal reaches the divider ballun, and then the input of both LDMOS transistors is given and the output of two transistors by the collector balloon reaches the output of the amplifier. We have simulated this design by using the Agilent Design System (ADS) software simulator with a gain more than 24 dB, the (Inter Modulation Distortion (IMD) signal has been attenuated from -29 to -52.5dBc and Power Added Effeciency (PAE) from 48 to 66% with 4-stage matching network consisting of capacitors and microstrips with a drain bias voltage of 28 volts and gate bias voltage of 2.86 volts in the frequency range 400 to 900 MHz. Eventually all of the circuit is designed on a printed circuit board. پرونده مقاله -
مقاله
3 - A New Design and Implementation of the Floating-Type Charge-Controlled Memcapacitor EmulatorMajlesi Journal of Telecommunication Devices , شماره 34 , سال 9 , بهار 2020Many researchers have done a lot on memcapacitor emulator circuits. It is due to the point that memcapacitor as a two-terminal element has not existed yet. These circuits must be developed their use in other applications and scientific fields, consequently many emulator چکیده کاملMany researchers have done a lot on memcapacitor emulator circuits. It is due to the point that memcapacitor as a two-terminal element has not existed yet. These circuits must be developed their use in other applications and scientific fields, consequently many emulators have been designed. The configuration of the proposed memcapacitor structure in this paper is very memorable due to the possibility of fabrication of a completely integrated proposed circuit. In this paper initially, the physical model implementation of memcapacitor has been simulated by Advance Design System (ADS) software, and then a new structure of memcapacitor emulator operating up to 256 Hz with available electronic devices is proposed. Experimental and practical results show the behaviour of memcapacitor as a memory device. پرونده مقاله -
مقاله
4 - A Novel Approach for Low Phase Noise Voltage Controlled Oscillator Design based on TSMC 0.18 um TechnologyMajlesi Journal of Telecommunication Devices , شماره 37 , سال 10 , زمستان 2021In this paper, a new structure of Voltage Control Oscillator (VCO) to reduce the phase noise using two plans of a variable voltage capacitor is proposed. The aim of the current paper is to analyse two structure of a completely integrated 3.7 GHz LC-VCO based on TSMC 0.1 چکیده کاملIn this paper, a new structure of Voltage Control Oscillator (VCO) to reduce the phase noise using two plans of a variable voltage capacitor is proposed. The aim of the current paper is to analyse two structure of a completely integrated 3.7 GHz LC-VCO based on TSMC 0.18 um technology. In the first plan for different voltages with variable voltage capacitors in this circuit can be achieved to a suitable phase noise of about 125 dB per Hz and in the second plan, a noise of -123 dB per Hz is achieved in the deviation frequency of 1 MHz. Also, the Figure of Merit (FOM) values for the first plan of -4/186 and for the second plan of –4/184 are achieved and the power consumption is 10 mW. پرونده مقاله -
مقاله
5 - Design and Nonlinear Analysis of a Novel MEMS-Based Resonator for Biomedical ApplicationsInternational Journal of Smart Electrical Engineering , شماره 2 , سال 11 , بهار 2022Complementary metal oxide semiconductor (CMOS) based microelectromechanical systems (MEMS) resonators are the main component of modern integrated systems that are designed and fabricated using CMOS composite layers. The design of these resonators, which are actuated ele چکیده کاملComplementary metal oxide semiconductor (CMOS) based microelectromechanical systems (MEMS) resonators are the main component of modern integrated systems that are designed and fabricated using CMOS composite layers. The design of these resonators, which are actuated electrostatically, is strongly dependent on the ambient temperature and the used materials. Important factors, such as structural features, actuator type, and the used materials should be considered in the design of micro resonators because they strongly affect the quality factor, power consumption and operating frequency of these devices. However, in designing micro resonators, electrostatic actuators are preferred over other actuator types due to their lower manufacturing cost, lower losses, and higher controllability. In this paper, first, some micro resonators are designed and their structures are then investigated. The micro resonators are mechanically analyzed to optimize their dimensions. A bias voltage of 0.1 V is applied to the micro resonators to investigate their feasibility for implantable biomedical applications. The switching time for a Zinc (Zn) movable plate is equal to 0.5 µs. In this paper, the role of device dimensions, Young’s modulus, switching time, material type, bridge displacement, and voltage (which is an important challenge in electrostatic resonators since it is usually high), as well as the effects of temperature on displacement are investigated. پرونده مقاله -
مقاله
6 - A Novel Technique for Low Power Consumption Based on Switch Capacitor in CMOS CircuitsInternational Journal of Smart Electrical Engineering , شماره 5 , سال 11 , پاییز 2022The share of static power from the total consumed power in deep submicron circuits is rapidly rising due to short channel effects. The present paper examines the recent techniques introduced for reducing leakage power and proposes a novel technique based on switched-cap چکیده کاملThe share of static power from the total consumed power in deep submicron circuits is rapidly rising due to short channel effects. The present paper examines the recent techniques introduced for reducing leakage power and proposes a novel technique based on switched-capacitor (SC) circuits for this purpose. The central concept consists of using two SCs on the route to PUN and PDN up to the output. Very high temperature stability and the ability to control the SC circuits using the clock frequency (〖 f〗_c) are among the benefits of the proposed concept. The introduced technique was implemented on NAND, NOR, and XOR logic gates and the C17 standard circuit. Next, the proposed model was simulated in HSPICE software with 32-nm BSIM4 (level-54 parameters) CMOS technology to investigate its leakage power, delay, surface area, and PDP factors. The results indicate the excellent leakage power reduction performance of this technique compared to previously introduced techniques. Implementing the presented circuit in various corners of the process and a subsequent temperature stability analysis demonstrated the high reliability of the proposed technique. پرونده مقاله